1. Field of the Invention
The present invention relates to a semiconductor device having a wiring line which is formed of Cu, and method of manufacturing the same.
2. Description of the Related Art
The more the structure of semiconductor devices becomes complicated, the more the structure of a wiring line included in the devices becomes sophisticated as well. Particularly, the multi-layer structure of a wiring line has become commonly used. In recent years, in order to lower the resistance of a wiring line and to increase the operational speed of devices, semiconductor devices, wherein wiring lines and plugs are formed of Cu and interlayer insulating films are formed of low-permittivity layers (Low-k layers), have been developed.
Cu is likely to enter the interlayer insulating films. Once Cu is diffused, a leakage current occurs between adjacent wiring lines. Hence, a layer what is so-called a barrier metal preventing the diffusion of Cu needs to be formed between the wiring line, the plug and the interlayer insulating films.
FIG. 9 is a cross section showing the structure of a semiconductor device having the barrier metal. The barrier metal included in this semiconductor device is formed of TaN, whereas interlayer insulating films are formed of organic polymer having low permittivity.
As described in FIG. 9, an SiN layer 22, an organic polymer layer 23, an SiN layer 27, an SiN layer 28, an organic polymer layer 29 and an SiN layer 33 are formed on a Cu wiring line 21 sequentially in this order.
A TaN layer 24 is formed on the inner surface of a via hole formed throughout the SiN layer 22, the organic polymer layer 23 and the SiN layer 27.
A seed layer 25 is formed over the TaN layer 24. The seed layer 25 is formed of Cu, and is a layer which serves as nuclei of crystallization for a plated layer 26 to grow, when to form the plated layer 26 with a plating.
The plated layer 26 is formed on the seed layer 25, so that the inside of the seed layer 25 is filled therewith. The plated layer 26 is formed of Cu, and serves as a plug together with the seed layer 25.
A TaN layer 30 is formed on the inner surface of an opening which is formed throughout the SiN layer 28, the organic polymer layer 29 and the SiN layer 33.
A seed layer 31 is formed above the TaN layer 30. The seed layer 31 is formed of Cu, and is a layer which serves as nuclei of crystallization for a plated layer 32 to grow, when to form the plated layer 32 with a plating.
The plated layer 32 is formed on the seed layer 31, so that the inside of the seed layer 31 is filled with the plated layer 32. The plated layer 32 is formed of Cu, and serves as a Cu wiring line together with the seed layer 31. This Cu wiring line is connected to a Cu wiring line 21 via the plug composed of the seed layer 25 and the plated layer 26.
FIGS. 10A to 10H are cross sections each showing a process for manufacturing the semiconductor device described in FIG. 9.
As illustrated in FIG. 10A, the SiN layer 22 which is 50 nm in thickness is formed on the Cu wiring line 21 with a CVD (Chemical Vapor Deposition) technique.
Then, for example, PAE (Poly Arylene Ether) as organic polymer is applied to the SiN layer 22 to a thickness of approximately 400 nm, and baked thereon. By doing this, as described in FIG. 10A, the organic polymer layer 23 is formed on the SiN layer 22.
As described in FIG. 10A, the SiN layer 27 which is 100 nm in thickness is formed on the organic polymer layer 23 with the CVD technique.
A photoresist 34 is formed on the SiN layer 27, and patterned as described in FIG. 10B.
Then, the SiN layer 27 is etched while using the photoresist 34 as a mask, as shown in FIG. 10C.
After this, as described in FIG. 10D, the photoresist 34 and the organic polymer layer 23 are etched with an O2 plasma etching process.
The SiN layers 22 and 27 are etched with an RF etching process, etc., thereby to form a via hole. As described in FIG. 10E, the TaN layer 24 which is 20 nm in thickness is formed on the inner surface of the via hole and on the surface of the SiN layer 27 with an ionization sputtering technique.
Then, as illustrated in FIG. 10F, the seed layer 25 which is 100 nm in thickness is formed over the TaN layer 24 with a sputtering technique.
As shown in FIG. 10G, the plated layer 26 which is 800 nm in thickness is formed over the seed layer 25 while being plated, so that the inside of the seed layer 25 is filled with the plated layer 26.
After this, as illustrated in FIG. 10H, the TaN layer 24, the seed layer 25 and the plated layer 26 are so polished as to expose the surface of the SiN layer 27 with a CMP (Chemical Mechanical Polishing) technique. By doing this, the plug composed of the seed layer 25 and the plated layer 26 can be formed.
Similarly to the above, after the SiN layer 28, the organic polymer layer 29 and the SiN layer 33 are formed, an opening is formed throughout the SiN layer 28, the organic polymer 29 and the SiN layer 33. The TaN layer 30, the seed layer 31 and the plated layer 32 are formed inside the opening, then the semiconductor device shown in FIG. 9 is finally completed.
Since the organic polymer layers 23 and 29 can not prevent the diffusion (penetration) of Cu, the TaN layers 24 and 30 are formed as a barrier metal.
In order to reliably prevent Cu from entering the organic polymer layers 23 and 29, the TaN layers 24 and 30 need to be formed thick (particularly to a thickness of 50 nm or more). Thus, the wiring line is hardly made small in size.
Besides, there is a large difference between the etching rate of TaN and that of Cu. Under such circumstances, if a CMP technique is applied both to the TaN layer 24 and the Cu layer (the seed layer 25 and the plated lay 26), dishing, recess or the like is likely to be formed in the Cu layer, as illustrated in FIG. 10H.
In the case of etching the SiN layers 22 or 28, Cu is attached to the inner wall of the via hole or the opening, as described in FIG. 11, and Cu may enter the organic polymer layers 23 or 29.
In a case where the plug and the Cu wiring line are formed in a dual damascene process, an aspect ratio of a hole, which has been formed to be filled with Cu, is high. Hence, a barrier metal to be formed on the periphery of the bottom of the hole may become quite thin, as described in FIG. 12.
In a case where the position in which the hole to be formed deviates from its appropriate position, another hole may be created in the interlayer insulating film which is adjacent to the lower wiring line, as illustrated in FIG. 12. The created hole is very narrow. Thus, on the periphery of the bottom of the hole, the barrier metal may be formed very thin or may not be formed.
Accordingly, if the barrier metal is formed very thin or is not formed, Cu is likely to be diffused, and a leakage current is likely to occur. As a result of the above, the semiconductor device may not properly operate.